Struct esp_idf_sys::spi_device_interface_config_t

#[repr(C)]
pub struct spi_device_interface_config_t {

    pub command_bits: u8,
    pub address_bits: u8,
    pub dummy_bits: u8,
    pub mode: u8,
    pub clock_source: spi_clock_source_t,
    pub duty_cycle_pos: u16,
    pub cs_ena_pretrans: u16,
    pub cs_ena_posttrans: u8,
    pub clock_speed_hz: c_int,
    pub input_delay_ns: c_int,
    pub spics_io_num: c_int,
    pub flags: u32,
    pub queue_size: c_int,
    pub pre_cb: transaction_cb_t,
    pub post_cb: transaction_cb_t,
}

@brief This is a configuration for a SPI slave device that is connected to one of the SPI buses.

Fields

command_bits: u8

< Default amount of bits in command phase (0-16), used when SPI_TRANS_VARIABLE_CMD is not used, otherwise ignored.

address_bits: u8

< Default amount of bits in address phase (0-64), used when SPI_TRANS_VARIABLE_ADDR is not used, otherwise ignored.

dummy_bits: u8

< Amount of dummy bits to insert between address and data phase

mode: u8

< SPI mode, representing a pair of (CPOL, CPHA) configuration:

• 0: (0, 0)
• 1: (0, 1)
• 2: (1, 0)
• 3: (1, 1)

clock_source: spi_clock_source_t

< Select SPI clock source, SPI_CLK_SRC_DEFAULT by default.

duty_cycle_pos: u16

< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128.

cs_ena_pretrans: u16

< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions.

cs_ena_posttrans: u8

< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)

clock_speed_hz: c_int

< Clock speed, divisors of the SPI clock_source, in Hz

input_delay_ns: c_int

< Maximum data valid time of slave. The time required between SCLK and MISO valid, including the possible clock delay from slave to master. The driver uses this value to give an extra delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing performance at high frequency (over 8MHz), it’s suggest to have the right value.

spics_io_num: c_int

< CS GPIO pin for this device, or -1 if not used

flags: u32

< Bitwise OR of SPI_DEVICE_* flags

queue_size: c_int

< Transaction queue size. This sets how many transactions can be ‘in the air’ (queued using spi_device_queue_trans but not yet finished using spi_device_get_trans_result) at the same time

pre_cb: transaction_cb_t

< Callback to be called before a transmission is started.

This callback is called within interrupt context should be in IRAM for best performance, see “Transferring Speed” section in the SPI Master documentation for full details. If not, the callback may crash during flash operation when the driver is initialized with ESP_INTR_FLAG_IRAM.

post_cb: transaction_cb_t

< Callback to be called after a transmission has completed.

This callback is called within interrupt context should be in IRAM for best performance, see “Transferring Speed” section in the SPI Master documentation for full details. If not, the callback may crash during flash operation when the driver is initialized with ESP_INTR_FLAG_IRAM.

Trait Implementations

impl Clone for spi_device_interface_config_t

fn clone(&self) -> spi_device_interface_config_t

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for spi_device_interface_config_t

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for spi_device_interface_config_t

fn default() -> Self

Returns the “default value” for a type.

impl Copy for spi_device_interface_config_t