Struct esp_idf_hal::interrupt::IsrCriticalSection

pub struct IsrCriticalSection(/* private fields */);

Implementations

impl IsrCriticalSection

#[link_section = ".iram1.interrupt_cs_new"]

pub const fn new() -> Self

Constructs a new IsrCriticalSection instance

#[link_section = ".iram1.interrupt_cs_enter"]

pub fn enter(&self) -> IsrCriticalSectionGuard<'_>

Disables all interrupts for the lifetime of the returned guard instance. This method supports nesting in that is safe to be called multiple times. This method is also safe to call from ISR routines.

NOTE: On dual-core esp32* chips, interrupts will be disabled only on one of the cores (the one where IsrCriticalSection::enter is called), while the other core will continue its execution. Moreover, if the same IsrCriticalSection instance is shared across multiple threads, where some of these happen to be scheduled on the second core (which has its interrupts enabled), the second core will then spinlock (busy-wait) in IsrCriticalSection::enter, until the first CPU releases the critical section and re-enables its interrupts. The second core will then - in turn - disable its interrupts and own the spinlock.

For more information, refer to https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/freertos-smp.html#critical-sections

Trait Implementations

impl Default for IsrCriticalSection

#[link_section = ".iram1.interrupt_cs_default"]

fn default() -> Self

Returns the “default value” for a type.

impl Send for IsrCriticalSection

impl Sync for IsrCriticalSection