pub const periph_interrput_t_ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE: periph_interrput_t = 40;
Expand description
< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL
pub const periph_interrput_t_ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE: periph_interrput_t = 40;
< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL