pub const emac_rmii_clock_gpio_t_EMAC_APPL_CLK_OUT_GPIO: emac_rmii_clock_gpio_t = 0;Expand description
@brief Output RMII Clock from internal APLL Clock available at GPIO0
@note GPIO0 can be set to output a pre-divided PLL clock (test only!). Enabling this option will configure GPIO0 to output a 50MHz clock. In fact this clock doesn’t have directly relationship with EMAC peripheral. Sometimes this clock won’t work well with your PHY chip. You might need to add some extra devices after GPIO0 (e.g. inverter). Note that outputting RMII clock on GPIO0 is an experimental practice. If you want the Ethernet to work with WiFi, don’t select GPIO0 output mode for stability.