Function esp_idf_svc::hal::sys::timer_set_divider

pub unsafe extern "C" fn timer_set_divider(
    group_num: u32,
    timer_num: u32,
    divider: u32,
) -> i32

@brief Set hardware divider of the source clock to the timer group. By default, the source clock is APB clock running at 80 MHz. For more information, please check Chapter Reset and Clock in Chip Technical Reference Manual. @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1 @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1] @param divider Timer clock divider value. The divider’s range is from from 2 to 65536.

@return - ESP_OK Success - ESP_ERR_INVALID_ARG Parameter error