Function esp_idf_svc::hal::sys::esp_cpu_set_watchpoint

pub unsafe extern "C" fn esp_cpu_set_watchpoint(
    wp_num: i32,
    wp_addr: *const c_void,
    size: usize,
    trigger: u32,
) -> i32

@brief Set and enable a hardware watchpoint on the current CPU

Set and enable a hardware watchpoint on the current CPU, specifying the memory range and trigger operation. Watchpoints will break/panic the CPU when the CPU accesses (according to the trigger type) on a certain memory range.

@note Overwrites previously set watchpoint with same watchpoint number. On RISC-V chips, this API uses method0(Exact matching) and method1(NAPOT matching) according to the riscv-debug-spec-0.13 specification for address matching. If the watch region size is 1byte, it uses exact matching (method 0). If the watch region size is larger than 1byte, it uses NAPOT matching (method 1). This mode requires the watching region start address to be aligned to the watching region size.

@param wp_num Hardware watchpoint number [0..SOC_CPU_WATCHPOINTS_NUM - 1] @param wp_addr Watchpoint’s base address, must be naturally aligned to the size of the region @param size Size of the region to watch. Must be one of 2^n and in the range of [1 … SOC_CPU_WATCHPOINT_MAX_REGION_SIZE] @param trigger Trigger type @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise