Available on crate feature
unstable
only.Expand description
§Stability
This API is marked as unstable and is only available when the unstable
crate feature is enabled. This comes with no stability guarantees, and could be changed
or removed at any time.
§Reading of eFuses (ESP32)
§Overview
The efuse
module provides functionality for reading eFuse data
from the ESP32
chip, allowing access to various chip-specific information
such as:
- MAC address
- Chip type, revision
- Core count
- Max CPU frequency
and more. It is useful for retrieving chip-specific configuration and identification data during runtime.
The Efuse
struct represents the eFuse peripheral and is responsible for
reading various eFuse fields and values.
§Examples
§Read data from the eFuse storage.
let mac_address = Efuse::read_base_mac_address();
println!(
"MAC: {:#X}:{:#X}:{:#X}:{:#X}:{:#X}:{:#X}",
mac_address[0],
mac_address[1],
mac_address[2],
mac_address[3],
mac_address[4],
mac_address[5]
);
println!("MAC address {:02x?}", Efuse::mac_address());
println!("Flash Encryption {:?}", Efuse::flash_encryption());
println!("Core Count {}", Efuse::core_count());
println!("Bluetooth enabled {}", Efuse::is_bluetooth_enabled());
println!("Chip type {:?}", Efuse::chip_type());
println!("Max CPU clock {:?}", Efuse::max_cpu_frequency());
Structs§
- A struct representing the eFuse functionality of the chip.
Enums§
- Representing different types of ESP32 chips.
Constants§
[]
Secure boot V1 is enabled for bootloader image[]
Secure boot V2 is enabled for bootloader image[]
ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE[]
ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE[]
ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE[]
ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE[]
True ADC reference voltage[]
BLOCK3 partially served for ADC calibration data[]
If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32’s max CPU frequency is rated for 160MHz. 240MHz otherwise[]
If set; the ESP32’s maximum CPU frequency has been rated[CHIP_VER_PKG]
Chip package identifier[CHIP_VER_PKG_4BIT]
Chip package identifier[]
bit is set to 1 for rev1 silicon[]
[CK8M_FREQ]
8MHz clock freq override[]
Efuse variable block length scheme {0: “NONE (BLK1-3 len=256 bits)”; 1: “3/4 (BLK1-3 len=192 bits)”; 2: “REPEAT (BLK1-3 len=128 bits) not supported”; 3: “NONE (BLK1-3 len=256 bits)”}[]
Disable ROM BASIC interpreter fallback[MAC_CUSTOM_CRC]
CRC8 for custom MAC address[CHIP_VER_DIS_APP_CPU]
Disables APP CPU[CHIP_VER_DIS_BT]
Disables Bluetooth[]
Disable flash cache in UART bootloader[]
Disable flash decryption in UART bootloader[]
Disable flash encryption in UART bootloader[]
[CHIP_VER_DIS_CACHE]
Disables cache[]
Flash encryption is enabled if this field has an odd number of bits set[ENCRYPT_CONFIG]
Flash encryption config (key tweak bits)[DISABLE_JTAG]
Disable JTAG[]
Usage of efuse block 3 (reserved)[MAC_FACTORY]
MAC address[MAC_FACTORY_CRC]
CRC8 for MAC address[MAC_CUSTOM]
Custom MAC address[MAC_CUSTOM_VER]
Version of the MAC field {1: “Custom MAC in BLOCK3”}[]
Disable reading from BlOCK1-3[]
rd_dis of ADC1_TP_HIGH[]
rd_dis of ADC1_TP_LOW[]
rd_dis of ADC2_TP_HIGH[]
rd_dis of ADC2_TP_LOW[]
rd_dis of BLK3_PART_RESERVE[RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1]
rd_dis of BLOCK1[RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2]
rd_dis of BLOCK2[RD_DIS.BLK3]
rd_dis of BLOCK3[]
rd_dis of CODING_SCHEME[RD_DIS.MAC_CUSTOM]
rd_dis of CUSTOM_MAC[RD_DIS.MAC_CUSTOM_CRC]
rd_dis of CUSTOM_MAC_CRC[RD_DIS.ENCRYPT_CONFIG]
rd_dis of FLASH_CRYPT_CONFIG[]
rd_dis of KEY_STATUS[RD_DIS.MAC_CUSTOM_VER]
rd_dis of MAC_VERSION[]
rd_dis of SECURE_VERSION[]
Secure version for anti-rollback[]
Override SD_CLK pad (GPIO6/SPICLK)[]
Override SD_CMD pad (GPIO11/SPICS0)[]
Override SD_DATA_1 pad (GPIO8/SPID)[]
read for SPI_pad_config_hd[]
Override SD_DATA_0 pad (GPIO7/SPIQ)[]
Disable UART download mode. Valid for ESP32 V3 and newer; only[]
This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)[]
[]
Efuse write disable mask[]
wr_dis of ABS_DONE_0[]
wr_dis of ABS_DONE_1[]
wr_dis of ADC1_TP_HIGH[]
wr_dis of ADC1_TP_LOW[]
wr_dis of ADC2_TP_HIGH[]
wr_dis of ADC2_TP_LOW[]
wr_dis of ADC_VREF[]
wr_dis of BLK3_PART_RESERVE[WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1]
wr_dis of BLOCK1[WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2]
wr_dis of BLOCK2[WR_DIS.BLK3]
wr_dis of BLOCK3[WR_DIS.CK8M_FREQ]
wr_dis of CLK8M_FREQ[]
wr_dis of CODING_SCHEME[]
wr_dis of CONSOLE_DEBUG_DISABLE[WR_DIS.MAC_CUSTOM]
wr_dis of CUSTOM_MAC[WR_DIS.MAC_CUSTOM_CRC]
wr_dis of CUSTOM_MAC_CRC[WR_DIS.CHIP_VER_DIS_APP_CPU]
wr_dis of DISABLE_APP_CPU[WR_DIS.CHIP_VER_DIS_BT]
wr_dis of DISABLE_BT[]
wr_dis of DISABLE_DL_CACHE[]
wr_dis of DISABLE_DL_DECRYPT[]
wr_dis of DISABLE_DL_ENCRYPT[WR_DIS.CHIP_VER_DIS_CACHE]
wr_dis of DIS_CACHE[]
wr_dis of FLASH_CRYPT_CNT[WR_DIS.ENCRYPT_CONFIG]
wr_dis of FLASH_CRYPT_CONFIG[WR_DIS.DISABLE_JTAG]
wr_dis of JTAG_DISABLE[]
wr_dis of KEY_STATUS[WR_DIS.MAC_FACTORY]
wr_dis of MAC[WR_DIS.MAC_FACTORY_CRC]
wr_dis of MAC_CRC[WR_DIS.MAC_CUSTOM_VER]
wr_dis of MAC_VERSION[WR_DIS.EFUSE_RD_DISABLE]
wr_dis of RD_DIS[]
wr_dis of SECURE_VERSION[]
wr_dis of SPI_PAD_CONFIG_CLK[]
wr_dis of SPI_PAD_CONFIG_CS0[]
wr_dis of SPI_PAD_CONFIG_D[]
wr_dis of SPI_PAD_CONFIG_Q[]
wr_dis of UART_DOWNLOAD_DIS[]
wr_dis of VOL_LEVEL_HP_INV[]
wr_dis of WR_DIS[WR_DIS.SDIO_FORCE]
wr_dis of XPD_SDIO_FORCE[]
wr_dis of XPD_SDIO_REG[WR_DIS.SDIO_TIEH]
wr_dis of XPD_SDIO_TIEH[SDIO_FORCE]
Ignore MTDI pin (GPIO12) for VDD_SDIO on reset[]
read for XPD_SDIO_REG[SDIO_TIEH]
If XPD_SDIO_FORCE & XPD_SDIO_REG {1: “3.3V”; 0: “1.8V”}